1. Field of the Invention
This invention relates generally to a parallel computer system, and more particularly to a parallel computer system using optical signal transfer procedure. Furthermore, this invention also relates to an optical interconnection block, processing block, system control block comprising a parallel computer system.
2. Description of the Prior Art
A supercomputer is a computer that performs vector and scalar computations at high speed. The supercomputer is usually supported by sophisticated software to execute these operations. On the other end of the scale, processors performing numerical operations at high speed, such as DSPs (Digital Signal Processors), and RISC (Reduced Instruction Set Computer) processors. DSPs are often used as digital signal processors, while RISC processors are generally used as processors for work stations. Both processors have essentially the same architecture in which high-speed operations are accomplished by separating the supply of data from that of instructions, and reducing the number of clock cycles required to execute operations. In order to reduce the time for decoding instructions, operations are performed with a small number of simplified instructions. This leads to reductions in the number of circuits and devices needed for higher-speed operations, permitting the space previously occupied by the circuits and devices to be used for cache memories and other devices. This contributes much to higher-speed operations. In both cases, operations are performed with a pipeline architecture. Some computers consist primarily of a single processing section having a multiplier unit (MU), and an arithmetic and logic unit (ALU), while some computers have a small number of parallel processing blocks. In both cases, a single-chip architecture is employed, in which a processing section, control section and a small number of memories are mounted on a single chip.
A parallel computer having multiple processing sections and performing parallel operations uses those RISC or CISC (Complex Instruction Set Computer) processors inter-connected by a special network (for example, multiple RISC transpurer processors with an N-cube connecting network). In a parallel computer, control of multiple processors is performed by one or more control units. In such a computer, operations are mostly performed in a SIMD (Single Instruction Multiple Data) mode where all processors perform the same operations with one common instruction. Some computers consisting of networks of this type accomplish high-speed operations by using several hundred thousands of simple processors, rather than using sophisticated processors, such as RISC. This type of computer, however, has failed to grow into general-purpose computers. The image processor is an example of such computers having essentially the same architecture and specific functions for image processing. Its simplest form is the image processing machine consisting of a 1-bit processor element. Aside from this type, most machines dedicated for image processing employ an architecture which performs special product-sum operations at high speed, for image processing such as spatial filtering.
Various architectures are adopted for the aforementioned computers according to the application fields thereof. The common characteristic of these architectures is the ability to execute high-speed processing in order to achieve a high cost-performance ratio. In current practice, a parallel processor architecture is adopted and a parallel and/or a pipeline operation are/is executed so as to carry out high-speed processing. This processor architecture is typically called superpipeline or superscaler. However, there are many problems to be solved in such computer system architectures, which have been discussed in many publications, for example in AT&T Technical Journal, Vol. 69 No. 6, Nov./Dec. 1990 and in IEEE Computer, Vol. 24, No. 9, pp. 18, 1991.
One such problem is clock skew. Clock cycles become inevitably shorter and shorter as higher-speed processing is pursuited. As a result, mismatch of synchronizing signals among gates may occur because synchronizing signals are passed through circuits having different length. These mismatches are not only caused in connections between processors comprising a parallel computer, but also within an arithmetic logic unit used in the processor to execute superpipeline or superscaler operations. Another problem occurs when data and instruction transfer buses include a plurality of electric conductive lines. When a plurality of processors are operated in parallel, these buses between processors are desirably operated in parallel to increase the effective band width of the data transfer channel. This results in complex bus configurations and interference of signals among lines in the buses. In the case of a circuit in a chip, the area occupied by lines of buses becomes larger and the processing area becomes smaller. Circuit and wiring technology is big problem to be overcome in current computer technology.
To overcome the aforementioned difficult problems in a current digital computer, intense research of optical computers is being carried out. An overview in this field may be found in Proc. IEEE, Vol. 72, No. 7, pp. 780, 1984. Typical architectures used are "Shadow Casting" described in Proc. IEEE Vol 72 pp. 787, 1984, "Symbolic Substitution" in Appl. Opt. Vol. 25, No. 18, pp. 3054, 1986 and "Logic Processing by Spatial Light Modulator" in Appl. Opt. Vol. 23, No. 19, pp. 3455, 1984 which are hereby incorporated by reference for their teachings on optical signal processing. Another approach to optical processing is a combined architecture of optics and digital processors, some of which are disclosed as a digital optical computer in Appl. Opt. Vol. 28, pp. 363, 1989. Concepts of the optical computer are very interesting, but it is not clear at this time whether these computers overcome the aforementioned difficult problems brought forward by electronic computers. Problems of clock skew, of complex wiring and of wide band width communication buses may be avoided with respect to arithmetic and logical processing parts in the optical computer. However, peripheral components of the optical computer supporting to these processing parts may cause same difficulties as one of the electronic computer. It is necessary to investigate its performance as total computer system.
A hybrid approach which uses optical fiber interconnection between electronic boards is described in Appl. Opt. Vol. 30, No. 7, pp. 2334, 1991. This approach makes use of transputers as parallel processors. Its optical interconnection along a back plane may be reconfigured. Electronic signals converted from optical signals at peripheral parts of boards are transferred to the transputers through electric links on boards like those found in a conventional computer. Therefore, the architecture of optical interconnection fails to escape from difficult problem caused by too many connector pins of a chip to circuits on the board.
As computers make more and more use of VLSI technology, requiring higher communications densities, optical interconnection become more and more important. Various concepts of optical interconnection have been proposed and tested. Typical ones are beam shuffle networks, crossover networks and free space interconnections. The free space interconnection has two main applications. The first is to selectively connect traveling beams in space to receiver components or devices by making use of hologram devices. This technique is disclosed in U.S. Pat. No. 4,135,706 issued on Dec. 21, 1987. The second application is to selectively connect devices by beams traveling in a dielectric layer, being reflected many times from both surfaces of the dielectric substrate plane to and being focused by hologram lenses to reach the appropriate devices. This procedure allows accurate positioning of light emitting and receiving devices by use of the well known fabrication technology for semiconductor chips, which is disclosed in U.S. Pat. No. 4,966,447 issued on Oct. 30, 1990. These free space interconnection methods are suitable for a computer system which is accommodated in a small housing compared with other methods. Due to the coherent nature of the laser beam and the hologram technology, selective interconnections can be achieved and dispersion of traveling beam in a dielectric substrate prevented. The final application targets mainly interconnection between boards while the latter procedure targets interconnection between semiconductor devices. In order to carry out the latter interconnection scheme, many supporting chips, laser arrays, drivers for laser arrays, sensor arrays and circuits or buses which send and receive al the signals necessary for electrically driving processing chips, should be mounted on a dielectric substrate. This is really equivalent to an interconnection between boards. A transparent glass substrate which is described as the best substrate in U.S. Pat. No. 4,966,447 may cause other problems when high frequency electric signals are transmitted between two chips.
In many of the aforementioned processors, data and control signals are transferred as electrical signals, and their inputs and outputs are controlled in accordance with instructions generated by the control section. Expansion of band width for input/output to improve operation speed and accuracy of arithmetic calculations is indispensable for higher-speed computing. It would lead to an increase in the number of input/output signals to the chip. With increases in band width, an increased number of input/output pins are needed on the board on which the chip is mounted. The number of pins that can be mounted on one chip, however, is limited to less than 500 with the current technological level.
Increasing the quantity of input/output signals to the chip would also inevitably result in complicated wirings on the circuit board. In high-speed operations involving high clock frequency, disturbances in signals or signal delays caused by wirings may cause operational errors, and limit the operational speed of the system.
Furthermore, the conventional processors are not capable of performing vector and scalar operations at high speed on a single chip. Although there exist supercomputers performing vector and scalar operations at high speed, they usually rely on separate chips. Processors of a DSP or RISC level have no appropriate architecture for performing vector and scalar operations at high speed.